1. Technical Field
Embodiments of the present disclosure generally relate to a post package repair device, and more particularly to a technology for outputting resource information of a fuse configured to repair a post package to an external part.
2. Related Art
A Dynamic Random Access Memory (DRAM) includes a plurality of memory cells arranged in the form of a matrix. However, if a defective or failed cell occurs in at least one memory cell from among a plurality of memory cells, it may be impossible for a semiconductor memory device to operate normally. So much so that the semiconductor memory device having the defective cell may be regarded as a defective product and abandoned. Semiconductor memory devices are being developed to have a higher degree of integration and to operate at a higher speeds. Thus, there is a higher possibility of causing or creating defective cells.
As a result, a production yield denoted by the ratio of a total number of chips to the number of normal chips, which is needed for deciding production costs of DRAMs, is gradually reduced. Therefore, in order to increase a production yield of semiconductor memory devices, many developers and companies are conducting intensive research into a method for fabricating highly-integrated semiconductor memory devices configured to operate at a higher speed and methods for efficiently repairing defective cells.
As an exemplary method for repairing the defective cell, a technology for embedding a repair circuit configured to replace a defective cell with a redundancy cell, into the semiconductor memory device has been widely used. Generally, the repair circuit includes redundancy columns/rows including redundancy memory cells arranged in rows and columns. The repair circuit may select the redundancy column/row to substitute for the defective column/row.
That is, if a row and/or column address signal for designating a defective cell is input to the repair circuit, the repair circuit may select the redundancy column/row instead of the defective column/row of a memory cell bank.
In order to recognize an address for designating a defective cell, the semiconductor memory device may include a plurality of fuses capable of being blown. The fuses are selectively blown so that an address of the defective cell can be programmed.
A method for repairing a defective cell of DRAMs is classified into a method (hereinafter referred to as a wafer repair method) for repairing the defective cell in a wafer state and a method (hereinafter referred to as a packaging repair method) for repairing the defective cell in a packaging state.
In this case, the wafer repairing method performs testing of memory cells of the semiconductor memory device at a wafer level. The wafer repairing method replaces a defective cell with a redundancy cell. The packaging repair method performs testing of memory cells of the semiconductor memory device at a package state. The packaging repair method replaces a defective cell with a redundancy cell at the package state. The above-mentioned case repairing of the defective cell is performed at a package state is referred to as a Post Package Repair (PPR) method.
However, according to a circuit structure capable of being simultaneously replaced with redundancy word lines of two banks during a post package repair (PPR) operation, fuse resources can be simultaneously reduced. In addition, it may be impossible to recognize the presence or absence of the remaining fuses available to the PPR operation. In addition, it may be impossible for the fuse structure allocated to each independent bank to maximally use a plurality of fuses, and the rupture operation may be repeatedly performed irrespective of the remaining fuses during the PPR operation.